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Advancing RISC-V performance: insights from the BZL internal Hackathon

Advancing RISC-V performance: insights from the BZL internal Hackathon

by Ariadna Rodriguez | Mar 19, 2026 | Uncategorized

BZL team during the Hackathon, showcasing a running Linpack instance on 2 nodes / 4 Ox cores. Last 26 February, the Barcelona Zettascale Lab team successfully concluded its internal RISC-V Hackathon, bringing together researchers and engineers to explore the latest...
Showcasing the success of the TC1 validation at Mobile World Congress

Showcasing the success of the TC1 validation at Mobile World Congress

by Ariadna Rodriguez | Mar 10, 2026 | Uncategorized

The Barcelona Zettascale Lab participated in this year’s Mobile World Congress (MWC), held in Barcelona from 2–5 March at Fira Gran Via. Following the successful announcement of the TC1 validation, which was first presented at the HiPEAC Conference in Krakow earlier...

Recent Posts

  • BZL brings engineering closer to the classroom to inspire secondary school students
  • BZL team advances RISC-V HPC capabilities at second internal hackathon
  • Advancing RISC-V performance: insights from the BZL internal Hackathon
  • Showcasing the success of the TC1 validation at Mobile World Congress
  • BSC strengthens Europe’s leadership in chip and memory innovation through joint research and training

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Este proyecto se impulsa por el Ministerio para la Transformación Digital y de la Función Pública, en el marco del Plan de Recuperación, Transformación y Resiliencia – Financiado por la Unión Europea – NextGenerationEU

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This project is promoted by the Ministry for Digital Transformation and the Civil Service, within the framework of the Recovery, Transformation and Resilience Plan – Funded by the European Union – NextGenerationEU

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