On 16 June 2026, the BZL project has held its final event titled “Towards Zettascale: advances at the Barcelona Zettascale Lab” in Madrid bringing together industrial and public stakeholders to present the major outcomes and reflect on the conclusions drawn from its development. The session marked the official closure of the project’s active phase, showcasing both technical achievements and key learnings across hardware, software, and ecosystem
Throughout the event, participants reviewed the main results obtained across the different work streams, highlighting the progression from initial concepts to implemented solutions. The presentations emphasized the maturity reached by the developed hardware and its methodologies, as well as their readiness for future chip designs, optimization, and future application in other BSC initiatives development.
Earlier that same day, and as part of the SARTECO conference, BZL experts also delivered the practical tutorial “How to gain experience in RISC-V with the BZL project,” offering participants hands-on experience with the project’s RISC-V ecosystem and reinforcing its commitment to knowledge transfer and community engagement.
Achievements of the project
The project successfully achieved its main objectives, delivering end-to-end results across both hardware and software development. This included the design, implementation, verification, and fabrication of two test chips (TC): Cinco Ranch TC1 (single-core) and Cinco Ranch TC2 (dual-core). In parallel, an entire software stack was developed for the RISC-V-based designs at BSC, enabling full system-level functionality and validation through meaningful use cases.
“Emerging computing architectures rely on a well-integrated software stack to unlock their full potential. A broad and evolving toolchain spanning multiple software domains is a key enabler for application development, performance, and adoption”, says Xavier Teruel, Software Leader at BZL and BSC Group Leader of the Best Practices for Performance and Programmability group.
Beyond the technical outcomes, BZL also established a strong academic hub aimed at attracting and training talent in chip design and RISC-V software development, strengthening the bridge between universities and European industry. By applying industry-inspired methodologies throughout the process, the initiative demonstrated a solid capacity to design advanced HPC and AI chips using leading-edge technology nodes, reinforcing its role in fostering innovation and technological excellence.
Talent and ecosystem growth
The project also delivered significant impact in terms of talent development and distribution. A total of 294 staff members were involved in the initiative, with strong talent retention at BSC and in national and European industry. The project further demonstrated strong talent attraction dynamics, with a balanced mix of international engineers (46.6%) and national engineers (53.4%), reinforcing its role as a magnet for both local and global expertise.
Project outcomes and future directions
The project has delivered a broad set of outcomes and will be further applied in other future initiatives such as DARE, HIGHER, MicroNanoSpain, ODE4EC, European HPC Centers of Excellence, etc., contributing to the consolidation of improved methodologies, strengthened infrastructures, and expanded technical expertise.
Looking ahead, several lines of future work have been identified, including the development of new hardware designs and implementations (such as Cinco Ranch TC3), enhanced operating system and software support for next-generation RISC-V hardware platforms, and further optimizations across the software stack. This includes advances in compilers (e.g., enhanced support for RISC-V vector), runtime systems and programming models, as well as numerical and AI/ML libraries and frameworks. Finally, the project points toward large-scale evaluation on multi-node systems, marking a significant step forward in addressing the challenges of distributed and network-scale computing.
“This project demonstrates Spain’s capacity, through coordinated public investment and scientific excellence, to build world-class capabilities in chip design, HPC, and RISC-V technologies, while creating and retaining highly skilled talent across academia and industry”, says Miquel Moretó , Hardware Leader at BZL and BSC HPC Architecture Research Area Director.
The event concluded with a shared assessment of the project’s overall impact, which was positively evaluated by participants. The BZL initiative closes having met its objectives and establishing a strong foundation for future innovation, collaboration, and technology development across the European HPC and chip design ecosystem.