BZL acerca RISC-V con un tutorial práctico en las Jornadas SARTECO
On Tuesday, June 16, as part of the SARTECO Conference, experts from the Barcelona Zettascale Lab (BZL) organized the tutorial “How to gain experience in RISC-V with the BZL project.” This activity helped bring the RISC-V ecosystem closer to attendees, while also...
BZL continues advancing RISC-V HPC capabilities through third Internal hackathon
On May 14, the Barcelona Zettascale Lab (BZL) team successfully concluded its third internal RISC-V hackathon, titled “Keep-on-Going,” continuing the progress achieved in previous editions and further advancing its experimental HPC ecosystem based on RISC-V...
BZL brings engineering closer to the classroom to inspire secondary school students
On March 26, Narcís Rodas, a researcher from the BZL project, participated in an event held at the Manyanet de Sant Andreu school in Barcelona, where former students shared their academic and professional journeys with secondary school students. These types of...
BZL team advances RISC-V HPC capabilities at second internal hackathon
On March 24, the BZL team successfully concluded its second internal hackathon, titled “Bring Your Code,” marking another milestone in the project’s efforts to advance high-performance computing on RISC-V platforms. Building on the achievements of the first hackathon,...
Advancing RISC-V performance: insights from the BZL internal Hackathon
BZL team during the Hackathon, showcasing a running Linpack instance on 2 nodes / 4 Ox cores. Last 26 February, the Barcelona Zettascale Lab team successfully concluded its internal RISC-V Hackathon, bringing together researchers and engineers to explore the latest...
Showcasing the success of the TC1 validation at Mobile World Congress
The Barcelona Zettascale Lab participated in this year’s Mobile World Congress (MWC), held in Barcelona from 2–5 March at Fira Gran Via.Following the successful announcement of the TC1 validation, which was first presented at the HiPEAC Conference in Krakow earlier...
BSC strengthens Europe’s leadership in chip and memory innovation through joint research and training
The Barcelona Supercomputing Center-Centro Nacional de Supercomputación is reinforcing Europe’s push toward next-generation computing through a training that brought together leading research and industry actors around a shared strategic vision: advancing chip...
Barcelona Zettascale Lab advances European technological sovereignty as Cinco Ranch TC1 chip passes validation
Tests confirm the robustness of the new open-source chip architecture, positioning the BSC-led lab among Europe’s leaders in advanced computing The Barcelona Zettascale Lab (BZL), a project led by the Barcelona Supercomputing Center – Centro Nacional de...
Barcelona Zettascale Lab showcases its progress in next-generation RISC-V–based HPC chip design at HiPEAC 2026
The presence at HiPEAC 2026 combined technological demonstrations, participation in key workshops, and a strong commitment to boosting European innovation in HPC.Several members of the Barcelona Supercomputing Center at the Barcelona Zettascale Lab booth at HiPEAC...
Barcelona Zettascale Lab strengthens its presence across key semiconductor and chip design events
Over the past months, the Barcelona Zettascale Lab (BZL) has actively participated in a range of leading events across the chip design, semiconductor, and high-performance computing (HPC) ecosystem. This presence reflects BZL’s commitment to advancing RISC-V,...