HiPEAC conference 2024 workshop: RISC-V: the cornerstone ISA for the next generation of HPC infrastructures

Coordinated by BSC and E4 engineering, the workshop titled “RISC-V: the cornerstone ISA for the next generation of HPC infrastructures” will bring together researchers from different disciplines, representatives from industries, computer architects, developers of scientific applications and users to describe the state of the art and outline the paths to be taken by RISC-V to make it the preferred ISA for HPC applications. In particular, the BZL coordinator Miquel Moretó will give a presentation titled “Towards a High Performance Manycore based on Lagarto Cores“