Barcelona, March 4, 2025 – Yesterday, the Barcelona Zettascale Lab (BZL) held its highly anticipated face-to-face meeting at the Ágora Room at UPC Barcelona. This key event brought together over 150 engineers from various teams to enhance communication and coordinate efforts toward the next tapeout of the high-performance RISC-V-based chip prototypes.
The day kicked off with a roadmap presentation by Miquel Moretó (BSC), highlighting significant milestones such as the success of the first tapeout and the challenges ahead for the second, which will integrate advanced technologies in collaboration with Intel. Each team then presented their progress, challenges, and strategies to optimize design quality and efficiency.
A major highlight of the event was the Quality Assessment Team presentation led by Rafael Gomà, emphasizing the adoption of best practices based on learnings from the first tapeout. Improvements in design verification and enhanced simulation platform functionalities were also key discussion points.
The meeting concluded with a session on best practices and next steps, reinforcing BZL’s commitment to innovation and excellence in developing processors for supercomputing.
Below are two images from the event:
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