The Barcelona Supercomputing Center (BSC) is pleased to announce the upcoming Europractice Training event, in collaboration with the Science and Technology Facilities Council (STFC), to be held in November 2024. This intensive five-day course offers a practical experience focused on digital and system design tools, with a special emphasis on SystemVerilog and RTL (Register Transfer Level) synthesis. It is ideal for both beginners and professionals who want to deepen their knowledge in these areas.
Event Details:
- Dates: November 25-29, 2024
- Location: Barcelona Supercomputing Center, C6 Building
- Target Audience: Primarily for BSC employees
- Instructors: Experts from the Europractice program at STFC
The content will range from introductory sessions on Verilog and SystemVerilog to advanced synthesis techniques, gate-level simulations, and finite state machine coding. The schedule is as follows:
- Day 1: Introduction to SystemVerilog, simulator fundamentals, and Verilog basics
- Day 2: Data types, arithmetic operations, testbenches, and debugging techniques
- Day 3: Best practices in synthesis and RTL coding
- Day 4: FSM coding and gate-level simulation
- Day 5: SystemVerilog data types and memory generation techniques
For more details, visit the Europractice Training Courses page or contact the training support team at training@bsc.es.
Recent Comments