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BSC strengthens Europe’s leadership in chip and memory innovation through joint research and training

BSC strengthens Europe’s leadership in chip and memory innovation through joint research and training

by Ariadna Rodriguez | Feb 25, 2026 | Uncategorized

The Barcelona Supercomputing Center-Centro Nacional de Supercomputación is reinforcing Europe’s push toward next-generation computing through a training that brought together leading research and industry actors around a shared strategic vision: advancing chip...
Barcelona Zettascale Lab advances European technological sovereignty as Cinco Ranch TC1 chip passes validation

Barcelona Zettascale Lab advances European technological sovereignty as Cinco Ranch TC1 chip passes validation

by Ariadna Rodriguez | Feb 10, 2026 | Uncategorized

Tests confirm the robustness of the new open-source chip architecture, positioning the BSC-led lab among Europe’s leaders in advanced computing The Barcelona Zettascale Lab (BZL), a project led by the Barcelona Supercomputing Center – Centro Nacional de...
Barcelona Zettascale Lab showcases its progress in next-generation RISC-V–based HPC chip design at HiPEAC 2026

Barcelona Zettascale Lab showcases its progress in next-generation RISC-V–based HPC chip design at HiPEAC 2026

by Ariadna Rodriguez | Feb 10, 2026 | Uncategorized

The presence at HiPEAC 2026 combined technological demonstrations, participation in key workshops, and a strong commitment to boosting European innovation in HPC. Several members of the Barcelona Supercomputing Center at the Barcelona Zettascale Lab booth at HiPEAC...

Recent Posts

  • Advancing RISC-V performance: insights from the BZL internal Hackathon
  • Showcasing the success of the TC1 validation at Mobile World Congress
  • BSC strengthens Europe’s leadership in chip and memory innovation through joint research and training
  • Barcelona Zettascale Lab advances European technological sovereignty as Cinco Ranch TC1 chip passes validation
  • Barcelona Zettascale Lab showcases its progress in next-generation RISC-V–based HPC chip design at HiPEAC 2026

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Este proyecto se impulsa por el Ministerio para la Transformación Digital y de la Función Pública, en el marco del Plan de Recuperación, Transformación y Resiliencia – Financiado por la Unión Europea – NextGenerationEU

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This project is promoted by the Ministry for Digital Transformation and the Civil Service, within the framework of the Recovery, Transformation and Resilience Plan – Funded by the European Union – NextGenerationEU

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