The presence at HiPEAC 2026 combined technological demonstrations, participation in key workshops, and a strong commitment to boosting European innovation in HPC.
Several members of the Barcelona Supercomputing Center at the Barcelona Zettascale Lab booth at HiPEAC 2026
On January 26, 27, and 28, the 21st edition of the HiPEAC Conference, el principal foro de redes de sistemas informáticos de Europa, en la que el Barcelona Zettascale Lab tuvo el placer de contribuir y formar parte.
the leading European forum for computer systems and architectures was held, with the Barcelona Zettascale Lab pleased to contribute and take part.
This year, the city of Krakow hosted the conference at the ICE Krakow venue, bringing together three intense days of workshops, presentations, tutorials, technical sessions, and poster exhibitions. The program focused on the key technologies currently being developed within the European advanced computing landscape.
At a time when digital sovereignty is becoming increasingly important, HiPEAC once again established itself as a benchmark networking space for companies, research centers, and academia. The conference also highlighted the latest advances in areas such as accelerated computing, hardware independence in compilation, and systems software.
Live demonstration of the TC1 chip
In this context, the Barcelona Zettascale Lab (BZL) actively contributed to the conference and hosted its own booth, where the project was presented and its role in strengthening European capabilities and expertise in the design and development of next-generation HPC chips, based on open RISC-V hardware and architectures, was showcased.
During the event, the successful bring-up of the TC1 chip was also presented, including a live demo at the booth. This milestone confirms the robustness of the architecture developed at BZL and represents a key step in technological innovation, reinforcing European sovereignty in advanced computing.
In addition to its presence in the exhibition area, the project participated in several workshops and technical sessions, such as “RISC-V: the cornerstone ISA for the next generation of HPC infrastructures”, “Parallel Programming and Run-Time Management Techniques for Many-core Architectures & Design Tools and Architectures for Multi-Core Embedded Computing Platforms (PARMA-DITAM)”, as well as poster presentations including “Driving RISC-V Innovation for HPC” and “A snapshot-based approach to verifying AI-written RTL with FPV”.
All these contributions helped strengthen the project’s visibility and impact within the conference, offering a more technical and detailed view of its evolution and the current state of developments.
Dr. Paul Carpenter presenting at Parallel Programming and Run-Time Management Techniques for Many-core Architectures & Design Tools and Architectures for Multi-Core Embedded Computing Platforms.
The space provided by HiPEAC was of great importance to the project, as it enabled the consolidation of collaborations, knowledge exchange with other key players in the European ecosystem, and the positioning of the Barcelona Zettascale Lab as a reference in high-performance computing based on open architectures.