Barcelona, June 2025 – At the Barcelona Zettascale Lab (BZL), we continue our efforts to advance the validation of high-tech chip prototypes. With this vision, Intel’s Hawk Canyon V2 board has been integrated into our research infrastructure, a key tool for the post-silicon validation process of the CincoRanch processor.
The Hawk Canyon V2 is a development board specifically designed to perform post-silicon validation of the CincoRanch processor, providing robust support for hardware testing, firmware development, and debugging. This integration ensures that our RISC-V based prototypes, developed with a focus on zettascale efficiency and sustainability, meet the highest standards of performance and reliability.
Relevant Technical Specifications of the Hawk Canyon V2:
- SoC Integration: Features a custom high-speed elastomer socket to house the CincoRanch processor.
- Memory Modules: Supports DDR5 SODIMM modules for main memory, and includes SPI-Flash memory chips for system boot and user data storage. Additionally, an integrated EEPROM stores board configuration.
- Power Supply: Uses a standard ATX power connector for board components and the processor, which are powered by 4 single-output switching regulators, 2 dual-output switching regulators, and 6 LDO linear regulators.
- Clock: The processor’s differential clock signal is generated with a 100 MHz oscillator integrated on the board, and SMP connectors are also available for an external clock input. There is a second 100 MHz differential clock oscillator for the PCIe interface.
- Peripherals: The processor has 8 PCIe Gen 5 channels for high-speed communication, connected to a standard PCIe connector. The board has 2 x 20-pin GPIO connectors, SPI interfaces for external flash memory, and UART and I3C/I2C interfaces for serial communication.
- Debugging and Configuration: Includes a JTAG interface for hardware debugging, VISA support, and an integrated FPGA for BIOS management and initial board configuration.
While the Hawk Canyon V2 board is not a direct development of BZL, it illustrates the complexity and rigor required in the post-silicon validation of high-performance chips. At the Barcelona Zettascale Lab, our focus on designing efficient and sustainable RISC-V prototypes for the zettascale era demands a deep understanding of these processes. We stay abreast of every advance in the ecosystem to apply the best methodologies in the verification of our own chips, ensuring that efficiency and sustainability translate into real and reliable performance.”
Francesc Moll, Synthesis and Physical Design of ICS Group Manager
This technological collaboration allows us to optimize testing and development processes, ensuring that future chips developed within the BZL framework are not only powerful but also energy-efficient and sustainable. This advancement underscores the academic and industrial impact of the BZL project in the global high-performance computing landscape.
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