Jornadas SARTECO

The SARTECO Workshops are a leading scientific meeting in Spain in the field of computer architecture and technology, organized by the Spanish Society of Computer Architecture and Technology (SARTECO). SARTECO This event brings together researchers, professionals, students, and industry representatives with the aim of sharing the latest advances in high-performance computing, processor architecture, parallel systems, and emerging computing technologies.

BZL will participate in these workshops with a tutorial titled “BZL Tutorial: How to Gain Experience in RISC-V with the BZL Project” on Tuesday, June 16, in room -1.A07, from 11:00 to 18:30.

This tutorial aims to help attendees become familiar with working with RISC-V. To this end, it offers an immersive, hands-on experience that will allow participants to gain knowledge using several tools such as QEMU and Gem5, as well as execute code on a complex design developed entirely by BSC within the BZL project. Attendees are expected to have basic knowledge of RISC-V.

Agenda:

  • 11:00 – 11:30h: Introduction to the BZL project, Miquel Moretó (principal investigator of the BZL project and director of the High-Performance Computer Architecture group at BSC)
  • 11:30 – 14:00h: How to simulate and analyze results with Gem5, Iván Fernández (BSC researcher)
  • 15:00 – 16:30h: Introduction to advanced BZL designs and access to the infrastructure – Daniel González and Ignacio Genovese (BSC)
  • 17:00 – 18:35h: How to run applications on advanced BZL designs – Daniel González and Ignacio Genovese (BSC)
  • 18:30 – 18:35h: Conclusion and closing remarks, Miquel Moretó (principal investigator of the BZL project and director of the High-Performance Computer Architecture group at BSC)

You can register for the tutorial through the following link: BZL Tutorial Registration Form

Register now