Barcelona, July 11, 2025 – As part of the Barcelona Zettascale Lab (BZL) project’s commitment to fostering expertise in cutting-edge computing technologies, BZL researcher Adrià Armejach from the Barcelona Supercomputing Center (BSC-CNS) and the Universitat Politècnica de Catalunya (UPC) led a comprehensive one-day course and hands-on session on gem5 simulation for RISC-V architectures. This event, held in Barcelona, brought together students and professionals eager to delve into the practical aspects of computer architecture simulation, a critical component in the design and development of next-generation processors.
The BZL project, a strategic initiative of the BSC-CNS, is at the forefront of Europe’s push for technological sovereignty in high-performance computing (HPC). By focusing on the open-source RISC-V instruction set architecture (ISA), the BZL aims to develop European processors for future zettascale supercomputers. This workshop aligns perfectly with the BZL’s mission to cultivate a robust ecosystem for RISC-V, from hardware design to software development and validation.
The session, titled RISC-V: 1-DAY COURSE FROM THEORY TO INDUSTRY provided attendees with a deep dive into gem5, a modular and flexible open-source computer architecture simulator. Armejach’s presentation guided participants through the fundamentals of gem5, its history, and its pivotal role in academic and industrial research. He emphasized the importance of simulation for evaluating new hardware designs before they are physically created, a practice that is both cost-effective and essential for the agile development of complex systems.
Participants learned about the intricacies of the gem5 software architecture, including its use of C++ for detailed models and Python for configuration and control. The hands-on portion of the course allowed attendees to use a pre-configured Docker container to run their own simulations, exploring the performance of vectorized code on a RISC-V processor model. This practical experience is invaluable for understanding the impact of design choices, such as vector register length (VLEN), on application performance.
The course is a testament to the BZL project’s dedication to knowledge sharing and building a skilled workforce for the European HPC ecosystem. By providing training on powerful simulation tools like gem5, the BZL is empowering the next generation of engineers and researchers to contribute to the future of European computing.
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