Over the past months, the Barcelona Zettascale Lab (BZL) has actively participated in a range of leading events across the chip design, semiconductor, and high-performance computing (HPC) ecosystem. This presence reflects BZL’s commitment to advancing RISC-V, fostering collaboration, and contributing to Europe’s technological sovereignty.
BSC Training Course: RISC-V principles for understanding how to freely develop new solutions
BZL contributed to this Barcelona Supercomputing Center training course, which focused on core concepts of computer architecture and their application to future RISC-V–based solutions. The course combined theory with a hands-on, learning-by-doing approach, enabling participants to explore both software and hardware layers of the RISC-V stack.
Through this initiative, students gained insight into the RISC-V ecosystem, BSC expertise, and the potential of open instruction set architectures to drive innovation.
As part of the program, Iván Fernández delivered the session Introduction to RISC-V in gem5, introducing participants to advanced simulation techniques
SC25: RISC-V in HPC Workshop
SC25 is one of the flagship global conferences for the high-performance computing community, offering a comprehensive technical program focused on best practices and emerging trends in HPC.
The Barcelona Zettascale Lab was represented by Petar Andrić, who took part in the RISC-V in HPC workshop. The workshop aimed to further consolidate the RISC-V HPC community and share the benefits of this open technology with domain scientists, tool developers, and supercomputing operators.
During the workshop, Andrić presented the research paper Enabling the syscall_intercept library for RISC-V, highlighting ongoing efforts to strengthen the RISC-V software ecosystem for HPC environments.
Bankinter Future Trends Forum
The Bankinter Future Trends Forum brings together international leaders from diverse disciplines to anticipate the major transformations shaping society, the economy, and technology. This edition focused on the future of the semiconductor industry, convening Spanish and international experts in chip manufacturing, computer architecture, and emerging materials.
The event featured high-profile speakers, including the former head of IMEC Europe, the former CEO of GlobalFoundries, and a former NASA director.
Osman Unsal, Group Manager of Computer Architecture for Parallel Paradigms, participated in a panel discussion addressing emerging materials and their potential to tackle AI’s energy challenges, as well as silicon photonics—a technology expected to see widespread adoption within the next five years.
Missió to Flanders by ACCIÓ
BZL also took part in a two-day mission to Flanders organized by ACCIÓ, together with the Departament de Recerca i Universitats and the Departament d’Unió Europea i Acció Exterior. The mission aimed to strengthen collaboration in research, innovation, and entrepreneurship in the field of microchips.
The visit offered an in-depth view of Flanders’ semiconductor ecosystem and strategy, while reinforcing ties with key stakeholders from research, industry, and public authorities. It also helped advance lab-to-fab collaboration pathways, bridging cutting-edge research with industrial manufacturing.
Within this context, Osman Unsal presented the work of the Barcelona Supercomputing Center and the Barcelona Zettascale Lab, outlining BZL’s objectives and its contribution to advanced chip design and manufacturing, as well as its broader role in positioning Europe as a global leader in HPC.
Chip Nation
The Barcelona Zettascale Lab participated in the III ChipNation Congress, held from December 3rd to 5th in Las Palmas de Gran Canaria. Organized by ASEMI together with local and regional authorities, the event brought together European and Spanish stakeholders from across the semiconductor ecosystem to discuss global trends, emerging innovations, and business opportunities.
BZL showcased its contribution to strengthening European capabilities in the design of next-generation HPC chips based on open hardware and RISC-V architectures, supporting Europe’s technological sovereignty. Together with other BSC-CNS-led initiatives, BZL highlighted ongoing efforts to reduce Europe’s dependency on third-party hardware technologies at its dedicated booth.
Miquel Moretó, coordinator of hardware activities at the Barcelona Zettascale Lab (BZL), also participated in the round table “RISC-V Opportunities in Spain”, where he discussed the latest challenges and opportunities within the European and Spanish RISC-V ecosystem and emphasized its strategic importance for European processor sovereignty.
Próximos eventos
HiPEAC 2026
The Barcelona Zettascale Lab will participate in HiPEAC 2026, the leading European forum for experts in computer architecture, programming models, compilers, and operating systems for general-purpose, embedded, and cyber-physical systems.
As part of the conference, a full-day workshop titled RISC-V: the cornerstone ISA for the next generation of HPC infrastructures will be held. The workshop will bring together researchers, industry representatives, computer architects, scientific application developers, and users to present the state of the art and discuss future directions for making RISC-V a mature and competitive ISA for HPC applications.