In line with our objectives, on July 30, 2025, BZL hosted a strategic meeting at the BSC Auditorium to plan the Register-Transfer Level (RTL) design freeze for CincoRanch TC2, scheduled for September.
On July 29, 2025, BZL received the first physical prototypes of the CincoRanch TC1 chip, a crucial milestone on our path towards zettascale computing. This achievement underscores our team’s dedication and success in advancing chip technology.
The Barcelona Zettascale Lab (BZL) is a cutting-edge project aiming to position Europe at the forefront of the global race for zettascale computing. We are dedicated to developing energy-efficient chip technologies based on the RISC-V architecture. Our mission is to drive innovation in the semiconductor field, collaborating closely with strategic partners to push the boundaries of current computing capabilities.
The primary goal of this meeting is to:
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Identify the specific needs of each team
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Discuss potential solutions to any issues or risks that may arise.
- Optimize efficiency in problem-solving, given the approaching deadline for the RTL freeze.
The teams involved in this crucial meeting include:
RTL Team
Design Verification Team
FPGA Technologies Team
Physical Design Team
DevOps Team
OS
SDV Team
We look forward to sharing further updates as we bring this processors to life and we integrate it with our HPC software stack.
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