The Barcelona Zettascale Lab (BZL) had a significant presence at ORConf 2025, Europe’s leading conference on open source hardware and software, held in Valencia from September 12-14. As a collaborator of the event, BZL reaffirms its commitment to the open hardware ecosystem and the RISC-V architecture, presenting its latest advancements in automating RTL design using artificial intelligence.
Our researcher, Dario Garcia Gasulla, delivered the talk “TuRTLe: A Unified and Open Evaluation of LLMs for RTL Generation.” In his presentation, Dario explained how BZL is developing a unified benchmarking system to evaluate Large Language Models (LLMs) for generating Register Transfer Level (RTL) code.
This innovative framework, a result of the collaboration between the hardware and artificial intelligence teams at BSC, aims to standardize the evaluation of AI in chip design—a crucial step toward improving the efficiency and quality of future semiconductors. The presentation generated significant interest among attendees, solidifying BZL’s leadership in applying AI to hardware design.
