BZL team during the Hackathon, showcasing a running Linpack instance on 2 nodes / 4 Ox cores.
Last 26 February, the Barcelona Zettascale Lab team successfully concluded its internal RISC-V Hackathon, bringing together researchers and engineers to explore the latest developments in open hardware architectures and high-performance computing.
The event focused on hands-on experimentation with RISC-V systems, operating systems, and application deployment. Participants worked with TC2-Ox platforms, including both dual-core and single-core configurations with VPU support, to compile and run applications in real-world conditions.
Despite some initial challenges in connecting all participants to FPGA resources, the team was able to overcome these issues and proceed with the planned activities. Attendees used cross-compilation techniques to build and run the Linpack benchmark with baseline MPI and BLIS libraries, later transitioning to optimized BLIS implementations. Some participants also began experimenting with their own benchmarks, including SDV-CAB and PyTorch workloads.+
Running the High-Performance Linpack (HPL) benchmark proved more complex. While successful executions were achieved—both with baseline and optimized BLIS—these were limited to specific user environments. Nonetheless, results demonstrated the system’s capabilities, particularly when leveraging optimized configurations on Ox cores with VPU acceleration.
One of the key observations from the hackathon was the clear performance and usability advantage of dual-core configurations over single-core setups, with significantly improved system responsiveness.
The session also included collaborative demonstrations, such as running Linpack across multiple nodes—reaching configurations of up to four Ox cores—highlighting the potential for scalable performance.
Looking ahead, the team identified four key areas for improvement, including connectivity, cross-compilation workflows, module provisioning, and VPU bitstream performance. These findings will inform the next edition of the hackathon, scheduled for the end of March, as the Barcelona Zettascale Lab continues to advance its work in RISC-V and high-performance computing.