The arrival of Test Chip 2 (TC2) marks the start of the bring-up phase, a key process for validating the dual-core RISC-V architecture developed by BZL
Last week, computer architecture experts received the Cinco Ranch Test Chip 2 (TC2) at the BSC offices, marking a new milestone in the development roadmap for processors based on the open RISC-V architecture.
After completing its submission for fabrication in January 2026, the arrival of TC2 allows the BZL expert team to move on to the next phase of the project: chip bring-up, a key process in which the manufactured silicon is powered on for the first time and its physical behavior is validated.
TC2 incorporates a dual-core architecture with three levels of on-chip cache memory and a vector processing unit compatible with the RISC-V Vector 1.0 (RVV 1.0) extension, featuring eight vector lanes equipped with four floating-point units (FPUs) each. The design has been optimized for Intel 18A technology and reaches a target frequency of 1.5 GHz.
The arrival of TC2 turns months of design and validation into a real chip that we can now put to the test. It’s a fundamental step toward our vision of next-generation European RISC-V processors.
During this new phase, the BZL team of experts will carry out the first experimental tests of the chip using the validation boards prepared for the TC2. These tests will make it possible to verify the correct functioning of the processor’s various blocks, evaluate its performance, and gather key information for future generations of the Cinco Ranch family.
