Validation and bring-up of the Test Chip 1
The two videos show the successful bring-up and validation of Test Chip 1 (TC1). They demonstrate that the chip is able to boot Linux and execute a representative set of computational benchmarks, confirming both functional correctness and system-level integration for two of the cores integrated in TC1.
Both systems run a Linux distribution generated with Buildroot, based on Linux kernel version 6.12.11. The software stack includes essential user-space packages, support for shared libraries, and standard command-line tools required to execute and validate workloads. The demonstration also shows how the operating system correctly detects and reports the supported RISC-V architectural extensions, further validating hardware–software compatibility.
TC1 Lagarto Ox
The first video (i.e., TC1-Lagarto-Ox-video) focuses on the Linux boot process running on Lagarto Ox, one of the three cores integrated into TC1. Lagarto Ox is a six-way out-of-order RISC-V processor fully designed and developed at BSC. The successful boot sequence confirms the correct interaction between the processor, memory subsystem, and peripheral infrastructure.
To validate computational capabilities, the video includes the execution of several numerical benchmarks: dot product, AXPY, sparse matrix–vector multiplication (SpMV), dense matrix–vector multiplication (GEMV), dense matrix–matrix multiplication (GEMM), fused multiply-add (FMA), and conjugate gradients (CG). The output of each benchmark is displayed, confirming functional correctness while also providing preliminary performance insights.
Additionally, this first video explores the impact of basic compiler optimization techniques—such as loop unrolling—illustrating how code-generation strategies influence execution efficiency. These examples highlight the importance of compiler optimizations in extracting performance from modern out-of-order RISC-V microarchitectures.
TC1 Lagarto Ka+VPU
The second video (i.e., TC1-Lagarto-Ka+VPU) highlights the execution of Lagarto Ka, another of the three cores integrated into TC1. Lagarto Ka is a two-way out-of-order RISC-V processor, also fully designed at BSC. A key distinguishing feature of Lagarto Ka is the integration of a Vector Processing Unit (VPU), which enables support for the RISC-V Vector Extension (RVV). This capability allows the processor to execute vector instructions and accelerate data-parallel workloads, extending its applicability to compute-intensive domains.
In this second demonstration, the numerical validation focuses on two representative kernels: the AXPY operation and dense matrix–matrix multiplication (GEMM). These benchmarks were selected to evaluate both scalar and vector execution paths, as well as to assess the behaviour of the Vector Processing Unit (VPU) integrated into Lagarto Ka. For both kernels, we explored different numerical precisions, executing the workloads with single-precision and double-precision floating-point elements.
These two videos demonstrate the successful operation of the cores, including system boot and workload execution, validating both scalar and vector functionality. In particular, they confirm the correct integration of the vector unit within the processor microarchitecture and its proper exposure through the software stack.
Overall, this demonstration represents an important step in the validation of TC1, confirming the correct operation of the processor, operating system, and software stack, while providing early performance indicators of the platform. It also provides further evidence of the functional maturity of TC1 and the versatility of its heterogeneous core designs.