Miquel Moretó presented the seminar “Designing HPC Architectures at BSC” on January 14 as part of the Future Computing Seminar Series, organized by ETH Zurich.
In his talk, Miquel provided an introduction to the different high-performance computing (HPC) architecture research projects led by the Barcelona Supercomputing Center (BSC). Since 2004, the BSC has been at the forefront of European efforts to develop HPC designs based on domestic technology. Within the framework of the European Mont-Blanc projects (2011–2021), and in close collaboration with Arm and Atos, the BSC implemented the first HPC cluster based on Arm technology.
More recently, the BSC has led the design, verification, and fabrication of RISC-V–based vector accelerators within the European Processor Initiative (EPI), as well as the development of general-purpose RISC-V processors in the context of the DRAC project. Since March 2025, the BSC has been coordinating the Digital Autonomy with RISC-V in Europe (DARE) project, which aims to develop prototypes of HPC and artificial intelligence systems based on industry-standard chiplets designed and developed in the European Union.
The seminar presented an overview of the main achievements of these projects, with a particular focus on efforts to accelerate HPC workloads through official and custom RISC-V ISA extensions. Finally, the talk addressed the current challenges in achieving European technological independence based on the open RISC-V instruction set architecture.