The Barcelona Zettascale Lab will take part in HiPEAC 2026, Europe’s leading forum for experts in computer architecture, programming models, compilers, and operating systems for general-purpose, embedded, and cyber-physical systems.
Within the conference programme, a full-day workshop entitled RISC-V: the cornerstone ISA for the next generation of HPC infrastructures will bring together researchers, industry representatives, computer architects, application developers, and users. The workshop will showcase the current state of the art and foster discussion on the future of RISC-V as a mature and competitive instruction set architecture for high-performance computing.
The Barcelona Zettascale Lab will also host a dedicated booth, where the team will present how the project is strengthening Europe’s skills and capabilities in the design and development of next-generation HPC chips based on open hardware and open architectures such as RISC-V.
In addition, Dr. Paul Carpenter, Senior Researcher at the Barcelona Supercomputing Center, will speak at the Parallel Programming and Run-Time Management Techniques for Many-core Architectures & Design Tools and Architectures for Multi-Core Embedded Computing Platforms (PARMA-DITAM) Workshop, where he will present research outcomes developed within the framework of the BZL.