REACH is an international conference from the Institution of Engineering and Technology (IET), focusing on the future of computer architecture. The two-day conference is an international forum for the latest advances in the computer architecture landscape, connecting leading voices in industry and academia for insightful discussions. REACH provides a meeting point for engineers, technologists and researchers shaping future computing horizons at this exciting time. The conference features expert speakers from around the world exploring key topics such as parallelization, future computer architectures, emerging computing technologies, and AI for computer architecture.
At REACH 2025, Miquel Moretó, HPC Architecture Research Area Director at the Barcelona Supercomputing Center (BSC), will present “Designing HPC Architectures at BSC” on 10th November 2025, 13:40–14:05 (Turing Lecture Theatre). His talk will explore BSC’s leading role in advancing European high-performance computing (HPC) through projects such as Mont-Blanc, EPI, and DRAC, focusing on the development of RISC-V-based processors and vector accelerators. Moretó will highlight efforts to strengthen European technological independence by accelerating HPC workloads using open, EU-developed architectures.
Abstract of the talk
Since 2004, the Barcelona Supercomputing Center is leading the European efforts to develop High Performance Computing (HPC) designs based on domestic technology. In the context of the Mont-Blanc European projects (2011-2021) and in close collaboration with Arm and Atos, BSC deployed the first HPC cluster based on Arm technology. More recently, BSC led the design, verification and fabrication of RISC-V-based vector accelerators in the context of the European Processor Initiative (EPI) and RISC-V general purpose processors in the context of the DRAC project. Since March 2025, BSC is leading the Digital Autonomy with RISC-V in Europe (DARE) project that will develop prototype HPC and AI systems based on EU-designed and developed industry-standard chiplets. In this talk, we will provide an overview of the main achievements in these projects, focusing on the efforts to accelerate HPC workloads with RISC-V official and custom ISA extensions. Finally, we will present current challenges to achieve European technological independence based on the RISC-V open instruction set architecture.
For more information, please visit the full programme here.