Hardware
The hardware team has two main objectives:
The design and development of high-performance hardware is a complex and costly task (in terms of time and resources) that is highly sensitive to errors. For this reason, BZL is committed to:
Designing and developing a high-performance architecture based on the RISC-V standard that meets the high-performance needs of current and future applications (processing large amounts of data in the shortest possible time, with the lowest possible energy consumption, and with the ability to adapt the design).
Offering a stable and incremental work platform that allows the software team to carry out their developments while the chip is not available.
Apply a multi-stage workflow (see image) to facilitate the detection and correction of errors in the early stages of design and implementation.
Minimizing human errors, both in the execution of highly repetitive simple tasks and in complex ones, by automating tasks through a continuous integration and continuous development process.
In line with the European and national strategy, BZL is committed to designing chips based on the open RISC-V standard to meet the growing computational and energy demands of modern applications in the HPC domain. RISC-V allows access to the entire instruction set and also enables the customization of instructions to solve specific problems, offering a range of possibilities for designing new specialized accelerators.
In this context, BZL’s chip designs will integrate multiple RISC-V processors, a vector processing unit (VPU), and a memory hierarchy tailored to the needs of the HPC domain.
Development Stages
Architectural Design: This involves designing the specifications for the main blocks of the design to be developed. It is a technical document (or documents) where the different work units, their requirements, dependencies, and performance are specified. The result of this stage is taken as a reference for the other stages of the workflow.
Design Verification: This work stage involves identifying errors in the RTL code and ensuring that the design meets the expected architectural specifications. The team uses verification techniques and tools such as UVM (Universal Verification Methodology) environments, Spike, code and functional coverage, assertions, and more.
Simulation: In this work stage, a model of the architecture is created using the Gem5 simulator to identify the viability of certain aspects of the system’s microarchitecture before investing time in its design.
Hardware Emulation: This stage leverages the properties of FPGAs (flexibility and reconfigurability) to validate the hardware before moving to the physical design stage. Additionally, the FPGA team is responsible for developing tools that enhance the usability of the devices and facilitate communication and observability of the system during execution.
RTL Development: In this work stage, the hardware description of each of the modules that will be part of the architecture (processors, accelerators, memory hierarchy, interconnection, etc.) is carried out, and the final system integration is also performed. SystemVerilog is used as the hardware description language for this purpose.
Physical Design and Manufacturing: This is the final stage of the design flow and consists of two phases. The first phase involves logical and physical synthesis, depending on the technology to be used for manufacturing. The second phase occurs once the chip is returned after manufacturing, where the team must “bring up” the chip to check its correct functioning and performance, and then produce a technical report based on the findings.